1. Field of the Invention
This invention relates to computing systems, and more particularly, to increasing the number of available instructions in an instruction set architecture wherein a new instruction includes an extra operand.
2. Description of the Relevant Art
Advances in computer architecture, semiconductor technology, and algorithm development have increased the complexity of microprocessor design while improving performance. Some instruction set architectures (ISAs) are reaching a limit in performance growth in an attempt to allow algorithm development to continue to advance. There are a few options for further increasing microprocessor performance. One option is to reduce the time required to execute individual instructions. However, clock periods are reaching a minimum limit due to semiconductor technology. A second option is to execute more instructions in parallel, but this option is expensive and increases the bandwidth pressure on the register file and bypass network. A third option is to increase the amount of work done by an instruction. Performing more work per instruction can be done in multiple ways and generally requires that more data per instruction is delivered to the execution units.
The third option has created demands to extend existing processor ISAs to support new algorithms by implementing new instructions. However, some ISAs have no method to identify more than 2 arithmetic operands in an instruction. There have been several attempts to solve this issue. For example, one method is fusing two separate micro instructions where each instruction identifies part of the required operands. Another method includes inferring additional operands based on the supplied operands. If register A is used as the first source operand, then the second operand may be assumed to come from register A+1. These methods still do not allow many arithmetic instructions to identify three operands and allow algorithms to continue to advance.
In view of the above, an efficient method for increasing the number of available instructions in an ISA wherein a new instruction includes an extra operand is desired.